Rainbow Electronics ATmega128L - Manual (Page 196)

196
ATmega128(L)
2467B–09/01
Overview of the TWI
Module The TWI module is comprised of several submodules, as shown in Figure 93. All regis-
ters drawn in a thick line are accessible through the AVR data bus.
Figure 93. Overview of the TWI Module
Scl and SDA Pins These pins interface the AVR TWI with the rest of the MCU system. The output drivers
contain a slew-rate limiter in order to conform to the TWI specification. The input stages
contain a spike suppression unit removing spikes shorter than 50 ns. Note that the inter-
nal pullups in the AVR pads can be enabled by setting the PORT bits corresponding to
the SCL and SDA pins, as explained in the I/O Port chapter. The internal pull-ups can in
some systems eliminate the need for external ones.
Bit Rate Generator Unit This unit controls the period of SCL when operating in a master mode. The SCL period
is controlled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in
the TWI Status Register (TWSR). Slave operation does not depend on Bit Rate or Pres-
caler settings, but the CPU clock frequency in the slave must be at least 16 times higher
than the SCL frequency. Note that slaves may prolong the SCL low period, thereby
reducing the average TWI bus clock period. The SCL frequency is generated according
to the following equation:
• TWBR = Value of the TWI Bit Rate Register
• TWPS = Value of the prescaler bits in the TWI Status Register
Bus Interface Unit This unit contains the Data and Address Shift register (TWDR), a START/STOP Con-
troller and Arbitration detection hardware. The TWDR contains the address or data
bytes to be transmitted, or the address or data bytes received. In addition to the 8-bit
TWDR, the Bus Interface Unit also contains a register containing the (N)ACK bit to be
transmitted or received. This (N)ACK register is not directly accessible by the applica-
tion software. However, when receiving, it can be set or cleared by manipulating the
TWI Unit
Address Register
(TWAR)
Address Match Unit
Address Comparator
Control Unit
Control Register
(TWCR)
Status Register
(TWSR)
State Machine and
Status control
SCL
Slew-rate
Control
Spike
Filter
SDA
Slew-rate
Control
Spike
Filter
Bit Rate Generator
Bit Rate Register
(TWBR)
Prescaler
Bus Interface Unit
START / STOP
Control
Arbitration detection Ack
Spike Suppression
Address/Data Shift
Register (TWDR)
SCL frequency
CPU Clock frequency
16 2(TWBR) 4
TW PS ⋅
+
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