Rainbow Electronics ATmega128L - Manual (Page 42)

42
ATmega128(L)
2467B–09/01
Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter
Idle Mode, stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, 2-
wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue
operating. This sleep mode basically halts clk
CPU
and clk
FLASH
, while allowing the other
clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as
internal ones like the Timer Overflow and USART Transmit Complete interrupts. If
wake-up from the Analog Comparator interrupt is not required, the Analog Comparator
can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-
tus register – ACSR. This will reduce power consumption in Idle Mode. If the ADC is
enabled, a conversion starts automatically when this mode is entered.
ADC Noise Reduction
Mode When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter
ADC Noise Reduction Mode, stopping the CPU but allowing the ADC, the external
interrupts, the 2-wire Serial Interface address watch, Timer/Counter0 and the Watchdog
to continue operating (if enabled). This sleep mode basically halts clk
I/O
, clk
CPU
, and
clk
FLASH
, while allowing the other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measure-
ments. If the ADC is enabled, a conversion starts automatically when this mode is
entered. Apart form the ADC Conversion Complete interrupt, only an external reset, a
watchdog reset, a brown-out reset, a 2-wire Serial Interface address match interrupt, a
Timer/Counter0 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt
on INT7:4, or an external interrupt on INT3:0 can wake up the MCU from ADC Noise
Reduction Mode.
Power-down Mode When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external oscillator is stopped, while the external
interrupts, the 2-wire Serial Interface address watch, and the Watchdog continue operat-
ing (if enabled). Only an external reset, a watchdog reset, a brown-out reset, a 2-wire
Serial Interface address match interrupt, an external level interrupt on INT7:4, or an
external interrupt on INT3:0 can wake up the MCU. This sleep mode basically halts all
generated clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to
“External Inter-
rupts” on page 84 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition
occurs until the wake-up becomes effective. This allows the clock to restart and become
stable after having been stopped. The wake-up period is defined by the same CKSEL
fuses that define the reset time-out period, as described in
“Clock Sources” on page 34.
Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter
Power-save Mode. This mode is identical to Power-down, with one exception:
If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set,
Timer/Counter0 will run during sleep. The device can wake up from either Timer Over-
f l o w o r O u t p u t C o m p a r e e v e n t f r o m T im e r/ C o u n t e r0 i f t h e c o r r e s p o n d i n g
Timer/Counter0 interrupt enable bits are set in TIMSK, and the global interrupt enable
bit in SREG is set.
If the asynchronous timer is NOT clocked asynchronously, Power-down mode is recom-
mended instead of Power-save Mode because the contents of the registers in the