Bit timer/counter register description, Timer/counter control register - tccr0, Bit timer/counter register description” on – Rainbow Electronics ATmega128L User Manual
Page 98: And figure 43 sh, Atmega128(l)
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98
ATmega128(L)
2467B–09/01
Figure 43. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with
Prescaler (f
clk_I/O
/8)
8-bit Timer/Counter
Register Description
Timer/Counter Control
Register - TCCR0
• Bit 7 - FOC0: Force Output Compare
The FOC0 bit is only active when the WGM bits specify a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is
written when operating in PWM mode. When writing a logical one to the FOC0 bit, an
immediate compare match is forced on the waveform generation unit. The OC0 output is
changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented
as a strobe. Therefore it is the value present in the COM01:0 bits that determines the
effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode
using OCR0 as TOP.
The FOC0 bit is always read as zero.
• Bit 6,3 - WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum
(TOP) counter value, and what type of waveform generation to be used. Modes of oper-
ation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare
match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See
52 and “Modes of Operation” on page 92.
OCFn
OCRn
TCNTn
(CTC)
TOP
TOP - 1
TOP
BOTTOM
BOTTOM + 1
clk
I/O
clk
Tn
(clk
I/O
/8)
Bit
7
6
5
4
3
2
1
0
FOC0
WGM00
COM01
COM00
WGM01
CS02
CS01
CS00
TCCR0
Read/Write
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Initial value
0
0
0
0
0
0
0
0