Voltage reference enable signals and start-up time, Watchdog timer, Atmega128(l) – Rainbow Electronics ATmega128L User Manual

Page 50

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50

ATmega128(L)

2467B–09/01

Voltage Reference Enable
Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used.
The start-up time is given in

Table 20. To save power, the reference is not always turned

on. The reference is on during the following situations:

1.

When the BOD is enabled (by programming the BODEN fuse).

2.

When the bandgap reference is connected to the Analog Comparator (by setting
the ACBG bit in ACSR).

3.

When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the
user must always allow the reference to start up before the output from the Analog Com-
parator or ADC is used. To reduce power consumption in power down mode, the user
can avoid the three conditions above to ensure that the reference is turned off before
entering power down mode.

Note:

1. Values are guidelines only. Actual values are TBD.

Watchdog Timer

The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1 Mhz.
This is the typical value at V

CC

= 5V. See characterization data for typical values at other

V

CC

levels. By controlling the Watchdog Timer prescaler, the Watchdog reset interval

can be adjusted as shown in

Table 22 on page 52. The WDR – Watchdog Reset –

instruction resets the Watchdog Timer. The Watchdog Timer is also reset when it is dis-
abled and when a chip reset occurs. Eight different clock cycle periods can be selected
to determine the reset period. If the reset period expires without another Watchdog
reset, the ATmega128 resets and executes from the Reset vector. For timing details on
the Watchdog reset, refer to

page 48.

To prevent unintentional disabling of the watchdog or unintentional change of time-out
period, 3 different safety levels are selected by the Fuses M103C and WDTON as
shown in Table 21. Safety level 0 corresponds to the setting in ATmega103. There is no
restriction on enabling the WDT in any of the safety levels. Refer to

“Timed Sequences

for Changing the Configuration of the Watch Dog Timer” on page 53 for details.

Table 20. Internal Voltage Reference Characteristics

(1)

Symbol

Parameter

Condition

Min

Typ

Max

Units

V

BG

Bandgap reference voltage

TBD

TBD

1.23

TBD

V

t

BG

Bandgap reference start-up time

TBD

40

70

µs

I

BG

Bandgap reference current
consumption

TBD

10

TBD

µA

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