Rainbow Electronics ATmega128L - Manual (Page 123)

123
ATmega128(L)
2467B–09/01
match between OCRnx and TCNTn when the counter decrements. The PWM frequency
for the output when using phase correct PWM can be calculated by the following
equation:
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCRnx register represents special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCRnx is set equal to
BOTTOM the output will be continuously low and if set equal to TOP the output will be
continuously high for non-inverted PWM mode. For inverted PWM the output will have
the opposite logic values.
Phase and Frequency Correct
PWM Mode The phase and frequency correct pulse width modulation, or phase and frequency cor-
rect PWM mode (WGMn3:0 = 8 or 9) provides a high resolution phase and frequency
correct PWM waveform generation option. The phase and frequency correct PWM
mode is, like the phase correct PWM mode, based on a dual-slope operation. The
counter counts repeatedly from BOTTOM (0x0000) to TOP and then from TOP to BOT-
TOM. In non-inverting compare output mode, the output compare (OCnx) is cleared on
the compare match between TCNTn and OCRnx while upcounting, and set on the com-
pare match while downcounting. In inverting compare output mode, the operation is
inverted. The dual-slope operation gives a lower maximum operation frequency com-
pared to the single-slope operation. However, due to the symmetric feature of the dual-
slope PWM modes, these modes are preferred for motor control applications.
The main difference between the phase correct, and the phase and frequency correct
PWM mode is the time the OCRnx register is updated by the OCRnx buffer register,
(see
Figure 52 and Figure 53).
The PWM resolution for the phase and frequency correct PWM mode can be defined by
either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to
0x0003), and the maximum resolution is 16-bit (ICRn or OCRnA set to MAX). The PWM
resolution in bits can be calculated using the following equation:
In phase and frequency correct PWM mode the counter is incremented until the counter
value matches either the value in ICRn (WGMn3:0 = 8), or the value in OCRnA
(WGMn3:0 = 9). The counter has then reached the TOP and changes the count direc-
tion. The TCNTn value will be equal to TOP for one timer clock cycle. The timing
diagram for the phase correct and frequency correct PWM mode is shown on
Figure 53.
The figure shows phase and frequency correct PWM mode when OCRnA or ICRn is
used to define TOP. The TCNTn value is in the timing diagram shown as a histogram for
illustrating the dual-slope operation. The diagram includes non-inverted and inverted
PWM outputs. The small horizontal line marks on the TCNTn slopes represent compare
matches between OCRnx and TCNTn. The OCnx interrupt flag will be set when a com-
pare match occurs.
f
OC nxPC PW M
f
clk_I/O
2 N TOP ⋅ ⋅
---------------------------- =
R
PFCPW M
TOP
1
+
( ) log
2 ( ) log
----------------------------------- =