Rainbow Electronics ATmega128L - Manual (Page 320)

320
ATmega128(L)
2467B–09/01
Figure 156. External Memory Timing (SRWn1 = 0, SRWn0 = 0
Figure 157. External Memory Timing (SRWn1 = 0, SRWn0 = 1)
ALE
T1 T2 T3
Write
Read
WR
T4
A15:8 Address Prev. addr.
DA7:0 Address Data Prev. data XX
RD
DA7:0 (XMBK = 0) Data Prev. data Address
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
ALE
T1 T2 T3
Write
Read
WR
T5
A15:8 Address Prev. addr.
DA7:0 Address Data Prev. data XX
RD
DA7:0 (XMBK = 0) Data Prev. data Address
System Clock (CLK
CPU
)
1
4
2
7
6
3a
3b
5
8 12
16
13
10
11
14
15
9
T4