Rainbow Electronics ATmega128L - Manual (Page 17)

17
ATmega128(L)
2467B–09/01
SRAM Data Memory The ATmega128 supports two different configurations for the SRAM data memory as
listed in
Table 1.
Figure 9 shows how the ATmega128 SRAM Memory is organized.
The ATmega128 is a complex microcontroller with more peripheral units than can be
supported within the 64 location reserved in the Opcode for the IN and OUT instructions.
For the Extended I/O space from $60 - $FF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used. The Extended I/O space does not exist when the
ATmega128 is in the ATmega103 compatibility mode.
In normal mode, the first 4352 Data Memory locations address both the Register file, the
I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations
address the Register file, the next 64 location the standard I/O memory, then 160 loca-
tions of Extended I/O memory, and the next 4096 locations address the internal data
SRAM.
In ATmega103 compatibility mode, the first 4096 Data Memory locations address both
the Register file, the I/O Memory and the internal data SRAM. The first 32 locations
address the Register file, the next 64 location the standard I/O memory, and the next
4000 locations address the internal data SRAM.
An optional external data SRAM can be used with the ATmega128. This SRAM will
occupy an area in the remaining address locations in the 64K address space. This area
starts at the address following the internal SRAM. The Register file, I/O, Extended I/O
and Internal SRAM uses the occupies the lowest 4352 bytes in normal mode, and the
lowest 4096 bytes in the ATmega103 compatibility mode (Extended I/O not present), so
when using 64KB (65536 bytes) of External Memory, 61184 Bytes of External Memory
are available in normal mode, and 61440 Bytes in ATmega103 compatibility mode. See
“External Memory Interface” on page 24 for details on how to take advantage of the
external memory map.
When the addresses accessing the SRAM memory space exceeds the internal data
memory locations, the external data SRAM is accessed using the same instructions as
for the internal data memory access. When the internal data memories are accessed,
the read and write strobe pins (PG0 and PG1) are inactive during the whole access
cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR
register.
Accessing external SRAM takes one additional clock cycle per byte compared to access
of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD,
PUSH and POP take one additional clock cycle. If the stack is placed in external SRAM,
interrupts, subroutine calls and returns take three clock cycles extra because the two-
byte program counter is pushed and popped, and external memory access does not
take advantage of the internal pipe-line memory access. When external SRAM interface
is used with wait-state, one-byte external access takes two, three, or four additional
clock cycles for one, two, and three wait-states respectively. Interrupt, subroutine calls
and returns will need five, seven, or nine clock cycles more than specified in the instruc-
tion set manual for one, two, and three wait-states.
Table 1. Memory Configurations
Configuration Internal SRAM Data Memory External SRAM Data Memory
Normal Mode 4096 up to 64K
ATmega103 Compatibility
Mode
4000 up to 64K