Rainbow Electronics ATmega128L - Manual (Page 124)

124
ATmega128(L)
2467B–09/01
Figure 53. Phase and Frequency Correct PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOVn) is set at the same timer clock cycle as the
OCRnx registers are updated with the double buffer value (at BOTTOM). When either
OCRnA or ICRn is used for defining the TOP value, the OCnA or ICFn flag set when
TCNTn has reached TOP. The interrupt flags can then be used to generate an interrupt
each time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the compare registers. If the TOP value is lower
than any of the compare registers, a compare match will never occur between the
TCNTn and the OCRnx.
As Figure 53 shows the output generated is, in contrast to the phase correct mode, sym-
metrical in all periods. Since the OCRnx registers are updated at BOTTOM, the length
of the rising and the falling slopes will always be equal. This gives symmetrical output
pulses and is therefore frequency correct.
Using the ICRn register for defining TOP works well when using fixed TOP values. By
using ICRn, the OCRnA register is free to be used for generating a PWM output on
OCnA. However, if the base PWM frequency is actively changed by changing the TOP
value, using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In phase and frequency correct PWM mode, the compare units allow generation of
PWM waveforms on the OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-
inverted PWM and an inverted PWM output can be generated by setting the COMnx1:0
to 3 (See
Table 60 on page 129). The actual OCnx value will only be visible on the port
pin if the data direction for the port pin is set as output (DDR_OCnx). The PWM
waveform is generated by setting (or clearing) the OCnx register at the compare match
between OCRnx and TCNTn when the counter increments, and clearing (or setting) the
OCnx register at compare match between OCRnx and TCNTn when the counter
OCRnx / TOP Update
and
TOVn Interrupt Flag Set
(Interrupt on Bottom)
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 2 3 4
TCNTn
Period
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)