Rainbow Electronics ATmega128L - Manual (Page 93)

93
ATmega128(L)
2467B–09/01
Figure 37. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by
using the OCF0 flag. If the interrupt is enabled, the interrupt handler routine can be used
for updating the TOP value. However, changing the TOP to a value close to BOTTOM
when the counter is running with none or a low prescaler value must be done with care
since the CTC mode does not have the double buffering feature. If the new value written
to OCR0 is lower than the current value of TCNT0, the counter will miss the compare
match. The counter will then have to count to its maximum value (0xFF) and wrap
around starting at 0x00 before the compare match can occur.
For generating a waveform output in CTC mode, the OC0 output can be set to toggle its
logical level on each compare match by setting the compare output mode bits to toggle
mode (COM01:0 = 1). The OC0 value will not be visible on the port pin unless the data
direction for the pin is set to output. The waveform generated will have a maximum fre-
quency of f
OC0
= f
clk_I/O
/2 when OCR0 is set to zero (0x00). The waveform frequency is
defined by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the normal mode of operation, the TOV0 flag is set in the same timer clock cycle
that the counter counts from MAX to 0x00.
Fast PWM Mode The fast pulse width modulation or fast PWM mode (WGM01:0 = 1) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM
option by its single-slope operation. The counter counts from BOTTOM to MAX then
restarts from BOTTOM. In non-inverting compare output mode, the output compare
(OC0) is cleared on the compare match between TCNT0 and OCR0, and set at BOT-
TOM. In inverting compare output mode, the output is set on compare match and
cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the
fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-
slope operation. This high frequency makes the fast PWM mode well suited for power
regulation, rectification, and DAC applications. High frequency allows physically small
sized external components (coils, capacitors), and therefore reduces total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX
value. The counter is then cleared at the following timer clock cycle. The timing diagram
for the fast PWM mode is shown in
Figure 38. The TCNT0 value is in the timing diagram
shown as a histogram for illustrating the single-slope operation. The diagram includes
TCNTn
OCn
(Toggle)
OCn Interrupt Flag Set
1 4 Period 2 3
(COMn1:0 = 1)
f
OC n
f
clk_I/O
2 N 1 OCRn +
( ) ⋅ ⋅
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