Rainbow Electronics ATmega128L - Manual (Page 114)

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ATmega128(L)
2467B–09/01
written to the ICRn register. When writing the ICRn register the high byte must be written
to the ICRnH I/O location before the low byte is written to ICRnL.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit
Registers” on page 109.
Input Capture Trigger Source The main trigger source for the input capture unit is the input capture pin (ICPn).
Timer/counter 1 can alternatively use the analog comparator output as trigger source for
the input capture unit. The analog comparator is selected as trigger source by setting
the analog comparator input capture (ACIC) bit in the analog comparator control and
status register (ACSR). Be aware that changing trigger source can trigger a capture.
The input capture flag must therefore be cleared after the change.
Both the input capture pin (ICPn) and the analog comparator output (ACO) inputs are
sampled using the same technique as for the Tn pin (
Figure 58 on page 138). The edge
detector is also identical. However, when the noise canceler is enabled, additional logic
is inserted before the edge detector, which increases the delay by 4 system clock
cycles. Note that the input of the noise canceler and edge detector is always enabled
unless the Timer/Counter is set in a waveform generation mode that uses ICRn to
define TOP.
An input capture can be triggered by software by controlling the port of the ICPn pin.
Noise Canceler The noise canceler improves noise immunity by using a simple digital filtering scheme.
The noise canceler input is monitored over 4 samples, and all 4 must be equal for
changing the output that in turn is used by the edge detector.
The noise canceler is enabled by setting the input capture noise canceler (ICNCn) bit in
Timer/Counter control register B (TCCRnB). When enabled the noise canceler intro-
duces additional 4 system clock cycles of delay from a change applied to the input, to
the update of the ICRn register. The noise canceler uses the system clock and is there-
fore not affected by the prescaler.
Using the Input Capture Unit The main challenge when using the input capture unit is to assign enough processor
capacity for handling the incoming events. The time between two events is critical. If the
processor has not read the captured value in the ICRn register before the next event
occurs, the ICRn will be overwritten with a new value. In this case the result of the cap-
ture will be incorrect.
When using the input capture interrupt, the ICRn register should be read as early in the
interrupt handler routine as possible. Even though the input capture interrupt has rela-
tively high priority, the maximum interrupt response time is dependent on the maximum
number of clock cycles it takes to handle any of the other interrupt requests.
Using the input capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed
after each capture. Changing the edge sensing must be done as early as possible after
the ICRn register has been read. After a change of the edge, the input capture flag
(ICFn) must be cleared by software (writing a logical one to the I/O bit location). For
measuring frequency only, the clearing of the ICFn flag is not required (if an interrupt
handler is used).