Data transfer and frame format, Transferring bits, Start and stop conditions – Rainbow Electronics ATmega128L User Manual

Page 191: Atmega128(l)

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191

ATmega128(L)

2467B–09/01

allowing the pull-up resistors to pull the line high. Note that all AVR devices connected to
the TWI bus must be powered in order to allow any bus operation.

The number of devices that can be connected to the bus is only limited by the bus
capacitance limit of 400 pF and the 7-bit slave address space. A detailed specification of
the electrical characteristics of the TWI is given in

“2-wire Serial Interface Characteris-

tics” on page 313. Two different sets of specifications are presented there, one relevant
for bus speeds below 100 kHz, and one valid for bus speeds up to 400 kHz.

Data Transfer and Frame
Format

Transferring Bits

Each data bit transferred on the TWI bus is accompanied by a pulse on the clock line.
The level of the data line must be stable when the clock line is high. The only exception
to this rule is for generating start and stop conditions.

Figure 86. Data Validity

START and STOP Conditions

The master initiates and terminates a data transmission. The transmission is initiated
when the master issues a START condition on the bus, and it is terminated when the
master issues a STOP condition. Between a START and a STOP condition, the bus is
considered busy, and no other master should try to seize control of the bus. A special
case occurs when a new START condition is issued between a START and STOP con-
dition. This is referred to as a REPEATED START condition, and is used when the
master wishes to initiate a new transfer without relinquishing control of the bus. After a
REPEATED START, the bus is considered busy until the next STOP. This is identical to
the START behaviour, and therefore START is used to describe both START and
REPEATED START for the remainder of this datasheet, unless otherwise noted. As
depicted below, START and STOP conditions are signalled by changing the level of the
SDA line when the SCL line is high.

Figure 87. START, REPEATED START and STOP Conditions

SDA

SCL

Data Stable

Data Stable

Data Change

SDA

SCL

START

STOP

REPEATED START

STOP START

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