Rainbow Electronics ATmega128L - Manual (Page 120)

120
ATmega128(L)
2467B–09/01
Figure 51. Fast PWM Mode, Timing Diagram
The Timer/Counter overflow flag (TOVn) is set each time the counter reaches TOP. In
addition the OCnA or ICFn flag is set at the same timer clock cycle as TOVn is set when
either OCRnA or ICRn is used for defining the TOP value. If one of the interrupts are
enabled, the interrupt handler routine can be used for updating the TOP and compare
values.
When changing the TOP value the program must ensure that the new TOP value is
higher or equal to the value of all of the compare registers. If the TOP value is lower
than any of the compare registers, a compare match will never occur between the
TCNTn and the OCRnx. Note that when using fixed TOP values the unused bits are
masked to zero when any of the OCRnx registers are written.
The procedure for updating ICRn differs from updating OCRnA when used for defining
the TOP value. The ICRn register is not double buffered. This means that if ICRn is
changed to a low value when the counter is running with none or a low prescaler value,
there is a risk that the new ICRn value written is lower than the current value of TCNTn.
The result will then be that the counter will miss the compare match at the TOP value.
The counter will then have to count to the MAX value (0xFFFF) and wrap around start-
ing at 0x0000 before the compare match can occur. The OCRnA register however, is
double buffered. This feature allows the OCRnA I/O location to be written anytime.
When the OCRnA I/O location is written the value written will be put into the OCRnA
buffer register. The OCRnA compare register will then be updated with the value in the
buffer register at the next timer clock cycle the TCNTn matches TOP. The update is
done at the same timer clock cycle as the TCNTn is cleared and the TOVn flag is set.
Using the ICRn register for defining TOP works well when using fixed TOP values. By
using ICRn, the OCRnA register is free to be used for generating a PWM output on
OCnA. However, if the base PWM frequency is actively changed (by changing the TOP
value), using the OCRnA as TOP is clearly a better choice due to its double buffer
feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the
OCnx pins. Setting the COMnx1:0 bits to 2 will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COMnx1:0 to 3 (See
Table 59 on
page 128). The actual OCnx value will only be visible on the port pin if the data direction
for the port pin is set as output (DDR_OCnx). The PWM waveform is generated by
TCNTn
OCRnx / TOP Update
and
TOVn Interrupt Flag Set
and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
1 7 Period 2 3 4 5 6 8
OCnx
OCnx
(COMnx1:0 = 2)
(COMnx1:0 = 3)