Digilent 6003-410-000P-KIT User Manual
Page 116
116
XUP Virtex-II Pro Development System
1-800-255-7778
UG069 (v1.0) March 8, 2005
Appendix E: User Constraint Files (UCF)
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## PINOUT AND IO DRIVE CHARACTERISTICS FOR THE CLOCKING
## SECTION OF THE XUP-V2PRO DEVELOPMENT SYSTEM
## REVISION C PRINTED CIRCUIT BOARD DEC 8 2004
## DEFINE THE CLOCKS FOR THE MGTs
NET "MGT_CLK_P" LOC = "F16";
NET "MGT_CLK_N" LOC = "G16";
NET "EXTERNAL_CLOCK_P" LOC = "G15";
NET "EXTERNAL_CLOCK_N" LOC = "F15";
NET "MGT_CLK_P" IOSTANDARD = LVDS_25;
NET "MGT_CLK_N" IOSTANDARD = LVDS_25;
NET "EXTERNAL_CLOCK_P" IOSTANDARD = LVDS_25;
NET "EXTERNAL_CLOCK_N" IOSTANDARD = LVDS_25;
NET "MGT_CLK_N" TNM_NET = "MGT_CLK_N";
TIMESPEC "TS_MGT_CLK_N" = PERIOD "MGT_CLK_N" 13.33 ns HIGH 50 %;
NET "MGT_CLK_P" TNM_NET = "MGT_CLK_P";
TIMESPEC "TS_MGT_CLK_P" = PERIOD "MGT_CLK_P" 13.33 ns HIGH 50 %;
## DEFINE THE SYSTEM CLOCKS
NET "SYSTEM_CLOCK" LOC = "AJ15";
NET "FPGA_SYSTEMACE_CLOCK" LOC = "AH15";
NET "ALTERNATE_CLOCK" LOC = "AH16";
NET "SYSTEM_CLOCK" IOSTANDARD = LVCMOS25;
NET "FPGA_SYSTEMACE_CLOCK" IOSTANDARD = LVCMOS25;
NET "ALTERNATE_CLOCK" IOSTANDARD = LVCMOS25;
NET "SYSTEM_CLOCK" TNM_NET = "SYSTEM_CLOCK";
TIMESPEC "TS_SYSTEM_CLOCK" = PERIOD "SYSTEM_CLOCK" 10.00 ns HIGH 50 %;
NET "FPGA_SYSTEMACE_CLOCK" TNM_NET = "FPGA_SYSTEMACE_CLOCK";
TIMESPEC "TS_FPGA_SYSTEMACE_CLOCK" = PERIOD "FPGA_SYSTEMACE_CLOCK"
31.25 ns HIGH 50 %;
## DEFINE THE DDR SDRAM CLOCK FEEDBACK LOOP
NET "CLK_FEEDBACK_OUT" LOC = "G23";
NET "CLK_FEEDBACK_IN" LOC = "C16";
NET "CLK_FEEDBACK_OUT" IOSTANDARD = SSTL2_II;
NET "CLK_FEEDBACK_IN" IOSTANDARD = SSTL2_II;