Table 2-15 – Digilent 6003-410-000P-KIT User Manual
Page 54
54
XUP Virtex-II Pro Development System
UG069 (v1.0) March 8, 2005
Chapter 2: Using the System
R
31
EXP_IO_35
R3
J2.41
LVTTL
33
EXP_IO_37
V1
J2.45
LVTTL
35
EXP_IO_39
T6
J2.49
LVTTL
37
EXP_IO_41
T4
J3.13
LVTTL
39
EXP_IO_43
U3
J3.17
LVTTL
2
VCC5VO
–
–
4
EXP_IO_8
N6
J1.27
LVTTL
6
EXP_IO_10
L5
J1.31
LVTTL
8
EXP_IO_12
M2
J1.35
LVTTL
10
EXP_IO_14
P9
J1.39
LVTTL
12
EXP_IO_16
M4
J1.43
LVTTL
14
EXP_IO_18
N1
J1.47
LVTTL
16
EXP_IO_20
P8
J2.11
LVTTL
18
EXP_IO_22
N4
J2.15
LVTTL
20
EXP_IO_24
P3
J2.19
LVTTL
22
EXP_IO_26
R8
J2.23
LVTTL
24
EXP_IO_28
P5
J2.27
LVTTL
26
EXP_IO_30
R2
J2.31
LVTTL
28
EXP_IO_32
R6
J2.35
LVTTL
30
EXP_IO_34
R4
J2.39
LVTTL
32
EXP_IO_36
U1
J2.43
LVTTL
34
EXP_IO_38
T5
J2.47
LVTTL
36
EXP_IO_40
T3
J3.11
LVTTL
38
EXP_IO_42
U2
J3.13
LVTTL
40
EXP_IO_44
U7
J3.19
LVTTL
Table 2-15:
Right Digilent Expansion Connector Pinout
J5
PIN
Signal
FPGA
Pin
Expansion
Header Pin
IO Type
1
GND
–
J1-4 EVEN PINS
–
3
VCC3V3
–
–
–
5
EXP_IO_45
T8
J3.21
LVTTL
Table 2-14:
Left Digilent Expansion Connector Pinout (Continued)
J5
PIN
Signal
FPGA
Pin
Expansion
Header Pin
IO Type