Digilent 6003-410-000P-KIT User Manual
Page 50
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50
XUP Virtex-II Pro Development System
UG069 (v1.0) March 8, 2005
Chapter 2: Using the System
R
41
EXP_IO_55
Y1
J6.15
LVTTL
43
EXP_IO_56
U7
J6.14
LVTTL
45
EXP_IO_57
U8
J6.17
LVTTL
47
EXP_IO_58
V5
J6.16
LVTTL
49
EXP_IO_59
V6
J6.19
LVTTL
51
VCC3V3
–
J5.3 J6.3
–
53
VCC3V3
–
J5.3 J6.3
–
55
VCC3V3
–
J5.3 J6.3
–
57
VCC2V5
–
–
–
59
VCC2V5
–
–
–
2
GND
–
J5.1 J6.1
–
4
GND
–
J5.1 J6.1
–
6
GND
–
J5.1 J6.1
–
8
GND
–
J5.1 J6.1
–
10
GND
–
J5.1 J6.1
–
12
GND
–
J5.1 J6.1
–
14
GND
–
J5.1 J6.1
–
16
GND
–
J5.1 J6.1
–
18
GND
–
J5.1 J6.1
–
20
GND
–
J5.1 J6.1
–
22
GND
–
J5.1 J6.1
–
24
GND
–
J5.1 J6.1
–
26
GND
–
J5.1 J6.1
–
28
GND
–
J5.1 J6.1
–
30
GND
–
J5.1 J6.1
–
32
GND
–
J5.1 J6.1
–
34
GND
–
J5.1 J6.1
–
36
GND
–
J5.1 J6.1
–
38
GND
–
J5.1 J6.1
–
40
GND
–
J5.1 J6.1
–
42
GND
–
J5.1 J6.1
–
Table 2-12:
Lower Middle Expansion Header Pinout (Continued)
J3
Pin
Signal
FPGA
Pin
Digilent
EXP Pin
IO Type
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