Digilent 6003-410-000P-KIT - Manual (Page 56)

56 www.xilinx.com XUP Virtex-II Pro Development System
UG069 (v1.0) March 8, 2005
Chapter 2: Using the System R
30 EXP_IO_72 AA3 J4.35 LVTTL
32 EXP_IO_74 W7 J4.39 LVTTL
34 EXP_IO_74 AB3 J4.43 LVTTL
36 JTAG_EXP_SEL – – LVTTL
38 FPGA_TCK G7 – LVTTL
40 FPGA_TDO F5 – LVTTL
Table 2-16: High-Speed Digilent Expansion Connector Pinout
J37
PIN
Signal
FPGA
Pin
Differential
Pair
I/O Type
A01 VCC3V3 – – –
A02 VCC3V3 – – –
A03 FPGA_TMS – – –
A04 HS_JTAG_EXP_SEL – – –
A05 HS_EXP_TDO – – –
A06 HS_IO_1 AF6 31P_3 LVTTL
A07 HS_IO_2 AE5 31N_3 LVTTL
A08 HS_IO_3 AB8 32P_3 LVTTL
A09 HS_IO_4 AB7 32N_3 LVTTL
A10 HS_IO_5 AE4 33P_3 LVTTL
A11 HS_IO_6 AE3 33N_3 LVTTL
A12 HS_IO_7 AF4 34P_3 LVTTL
A13 HS_IO_8 AF3 34N_3 LVTTL
A14 HS_IO_9 AC6 35P_3 LVTTL
A15 HS_IO_10 AC5 35N_3 LVTTL
A16 HS_IO_11 AF2 36P_3 LVTTL
A17 HS_IO_12 AF1 36N_3 LVTTL
A18 HS_IO_13 AD4 37P_3 LVTTL
A19 HS_IO_14 AD3 37N_3 LVTTL
A20 HS_IO_15 AA8 38P_3 LVTTL
A21 HS_IO_16 AA7 38N_3 LVTTL
A22 HS_IO_17 AE2 39P_3 LVTTL
Table 2-15: Right Digilent Expansion Connector Pinout (Continued)
J5
PIN
Signal
FPGA
Pin
Expansion
Header Pin
IO Type