Digilent 6003-410-000P-KIT - Manual (Page 25)

XUP Virtex-II Pro Development System www.xilinx.com 25
UG069 (v1.0) March 8, 2005
Using the DIMM Module DDR SDRAM R
Read and Write accesses to the DDR SDRAM are burst oriented: accesses start at a selected
location and continue for a programmed number of locations in a programmed sequence.
Accesses begin with the registration of an Active command, which is followed by a Read or
Write command. The address bits registered coincident with the Read or Write command
are used to select the bank and starting column location for the burst address.
DDR SDRAM provides for 2, 4, 8, or full-page programmable Read or Write burst lengths.
The allowable burst lengths depend on the specific DDR SDRAM used on the DIMM
module. This information can be obtained from the serial presence detect (SPD) EEPROM.
An auto-precharge function can be enabled to provide a self-timed precharge that is
initiated at the end of the burst sequence. As with standard SDRAMs, the pipelined
multibank architecture of DDR SDRAMs allows for concurrent operation, thereby,
providing high effective bandwidth by hiding row precharge and activation time.
The modules incorporate a serial presence detect (SPD) function implemented using a
2048-bit EEPROM. The first 128 bytes of the EEPROM are programmed by the module
manufacturer to identify the module type and various SDRAM timing parameters. The
remaining 128 bytes of EEPROM are available for use as non-volatile memory. The
EEPROM is accessed using a standard I
2 C bus protocol using the SDRAM_SCL (serial
clock) and SDRAM_SDA (serial data) signals.
Data on the SDRAM_SDA signal can change only when the clock signal SDRAM_SCL is
low. Changes in the SDRAM_SDA data signal when SDRAM_SCL is high; this indicates a
start or stop bit condition as shown in
Figure 2-6 . A high-to-low transition of
SDRAM_SDA when SDRAM_SCL is high indicates a start bit condition, the start of all
commands. A low-to-high transition of SDRAM_SDA when SDRAM_ SCL is high
indicates a stop bit condition, terminating the command placing the SPD device into a low
power mode.
All commands commence with a start bit, followed by eight data bits. The transmitting
device, either the bus master or slave, releases the bus after transmitting eight bits. During
the ninth clock cycle, the receiver pulses the SDA data signal low to acknowledge that it
received the eight bits of data as shown in
Figure 2-7 .
Figure 2-6: Definition of Start and Stop Conditions
SDRAM_SCL
SDRAM_SDA
START BIT STOP BIT
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