Table 2-13 – Digilent 6003-410-000P-KIT User Manual
Page 51
XUP Virtex-II Pro Development System
51
UG069 (v1.0) March 8, 2005
Using the Expansion Headers and Digilent Expansion Connectors
R
44
GND
–
J5.1 J6.1
–
46
GND
–
J5.1 J6.1
–
48
GND
–
J5.1 J6.1
–
50
GND
–
J5.1 J6.1
–
52
GND
–
J5.1 J6.1
–
54
GND
–
J5.1 J6.1
–
56
GND
–
J5.1 J6.1
–
58
GND
–
J5.1 J6.1
–
60
GND
–
J5.1 J6.1
–
Table 2-13:
Bottom Expansion Header Pinout
J4
Pin
Signal
FPGA
Pin
Digilent
EXP Pin
IO Type
1
VCC5V0
–
J5.2 J6.2
–
3
VCC5V0
–
J5.2 J6.2
–
5
VCC3V3
–
J5.3 J6.3
–
7
VCC3V3
–
J5.3 J6.3
–
9
VCC3V3
–
J5.3 J6.3
–
11
EXP_IO_60
Y2
J6.18
LVTTL
13
EXP_IO_61
AA2
J6.21
LVTTL
15
EXP_IO_62
V7
J6.20
LVTTL
17
EXP_IO_63
V8
J6.23
LVTTL
19
EXP_IO_64
W3
J6.22
LVTTL
21
EXP_IO_65
W4
J6.25
LVTTL
23
EXP_IO_66
AA1
J6.24
LVTTL
25
EXP_IO_67
AB1
J6.27
LVTTL
27
EXP_IO_68
W5
J6.26
LVTTL
29
EXP_IO_69
W6
J6.29
LVTTL
31
EXP_IO_70
Y4
J6.28
LVTTL
33
EXP_IO_71
Y5
J6.31
LVTTL
35
EXP_IO_72
AA3
J6.30
LVTTL
37
EXP_IO_73
AA4
J6.33
LVTTL
Table 2-12:
Lower Middle Expansion Header Pinout (Continued)
J3
Pin
Signal
FPGA
Pin
Digilent
EXP Pin
IO Type