Digilent 6003-410-000P-KIT User Manual
Page 57
XUP Virtex-II Pro Development System
57
UG069 (v1.0) March 8, 2005
Using the Expansion Headers and Digilent Expansion Connectors
R
A23
HS_IO_18
AE1
39N_3
LVTTL
A24
HS_IO_19
AB6
40P_3
LVTTL
A25
HS_IO_20
AB5
40N_3
LVTTL
A26
HS_IO_21
Y8
41P_3
LVTTL
A27
HS_IO_22
Y7
41N_3
LVTTL
A28
HS_IO_23
AD2
42P_3
LVTTL
A29
HS_IO_24
AD1
42N_3
LVTTL
A30
HS_IO_25
L7
41P_2
LVTTL
A31
HS_IO_26
L8
41N_2
LVTTL
A32
HS_IO_27
G1
40P_2
LVTTL
A33
HS_IO_28
G2
40N_2
LVTTL
A34
HS_IO_29
G3
39P_2
LVTTL
A35
HS_IO_30
G4
39N_2
LVTTL
A36
HS_IO_31
J5
38P_2
LVTTL
A37
HS_IO_32
J6
38P_2
LVTTL
A38
HS_IO_33
F1
37P_2
LVTTL
A39
HS_IO_34
F2
37P_2
LVTTL
A40
HS_IO_35
F3
36P_2
LVTTL
A41
HS_IO_36
F4
36N_2
LVTTL
A42
HS_IO_37
K7
35P_2
LVTTL
A43
HS_IO_38
K8
35N_2
LVTTL
A44
HS_IO_39
E1
34P_2
LVTTL
A45
HS_IO_40
E2
34N_2
LVTTL
A46
GND
–
–
–
A47
HS_CLKOUT
E4
33N_2
LVTTL
A48
GND
–
–
–
A49
VCC5V0
–
–
–
A50
VCC5V0
–
–
–
B01
SHIELD
–
–
–
B02
GND
–
–
–
B03
LS_EXP_FPGA_TDO
–
–
–
Table 2-16:
High-Speed Digilent Expansion Connector Pinout (Continued)
J37
PIN
Signal
FPGA
Pin
Differential
Pair
I/O Type