Digilent 6003-410-000P-KIT - Manual (Page 46)

46 www.xilinx.com XUP Virtex-II Pro Development System
UG069 (v1.0) March 8, 2005
Chapter 2: Using the System R
45 EXP_IO_17 M3 J5.13 LVTTL
47 EXP_IO_18 N1 J5.14 LVTTL
49 EXP_IO_19 P1 J5.15 LVTTL
51 VCC3V3 – J5.3 J6.3 –
53 VCC3V3 – J5.3 J6.3 –
55 VCC3V3 – J5.3 J6.3 –
57 VCC2V5 – – –
59 VCC2V5 – – –
2 GND – J5.1 J6.1 –
4 GND – J5.1 J6.1 –
6 GND – J5.1 J6.1 –
8 GND – J5.1 J6.1 –
10 GND – J5.1 J6.1 –
12 GND – J5.1 J6.1 –
14 GND – J5.1 J6.1 –
16 GND – J5.1 J6.1 –
18 GND – J5.1 J6.1 –
20 GND – J5.1 J6.1 –
22 GND – J5.1 J6.1 –
24 GND – J5.1 J6.1 –
26 GND – J5.1 J6.1 –
28 GND – J5.1 J6.1 –
30 GND – J5.1 J6.1 –
32 GND – J5.1 J6.1 –
34 GND – J5.1 J6.1 –
36 GND – J5.1 J6.1 –
38 GND – J5.1 J6.1 –
40 GND – J5.1 J6.1 –
42 GND – J5.1 J6.1 –
44 GND – J5.1 J6.1 –
46 GND – J5.1 J6.1 –
Table 2-10: Top Expansion Header Pinout (Continued)
J1
Pin
Signal
FPGA
Pin
Digilent
EXP Pin
I/O Type