Digilent 6003-410-000P-KIT User Manual
Page 8
XUP Virtex-II Pro Development System
UG069 (v1.0) March 8, 2005
Figure A-8: Programming the FPGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Appendix B: Programming the Platform FLASH PROM User Area
Figure B-1: Operation Mode Selection: Prepare Configuration Files . . . . . . . . . . . . . . . . . 77
Figure B-2: Selecting PROM File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure B-3: Selecting a PROM with Design Revisioning Enabled . . . . . . . . . . . . . . . . . . . 79
Figure B-4: Selecting an XCF32P PROM with Two Revisions . . . . . . . . . . . . . . . . . . . . . . . 79
Figure B-5: Adding a Device File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure B-6: Adding the Design File to Revision 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Figure B-7: iMPACT Startup Clock Warning. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure B-8: Adding the Design File to Revision 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure B-9: Generating the MCS File. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure B-10: Switching to Configuration Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure B-11: Initializing the JTAG Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure B-12: Assigning the MCS File to the PROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure B-13: Programming the PROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure B-14: PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure B-15: iMPACT PROM Programming Transcript Window . . . . . . . . . . . . . . . . . . . . 85
Appendix C: Restoring the Golden FPGA Configuration
Figure C-1: Operation Mode Selection: Configure Devices . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure C-2: Selecting Boundary Scan Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure C-3: Boundary Scan Mode Selection: Automatically Connect to the Cable
and Identify the JTAG Chain
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure C-4: Assigning New PROM Configuration File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure C-5: Erasing the Existing PROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure C-6: Transcript Window for the Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure C-7: Selecting the Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure C-8: PROM Programming Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure C-9: iMPACT PROM Programming Transcript Window . . . . . . . . . . . . . . . . . . . . . 95
Appendix D: Using the Golden FPGA Configuration for System Self-
Figure D-1: XUP Virtex-II Pro Development System BIST Block Diagram . . . . . . . . . . . 97
Figure D-2: Built-In Self-Test Main Menu . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure D-3: Testing the SATA 0 HOST to SATA 1 TARGET Connection. . . . . . . . . . . . 103
Figure D-4: Testing the SATA 2 HOST to SATA 1 TARGET Connection. . . . . . . . . . . . 103
Figure D-5: Selecting the SATA Port Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure D-6: Selecting the Specific SATA Port to Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure D-7: Resetting the MGTs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure D-8: No Link Established Error Message. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure D-9: SATA Test Running . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Figure D-10: SATA Loopback Test PASSED . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106