Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 102)

92 Serial I/O Models
Example
// In this example I/O pin IO_7 is connected to a
// ~Data_valid signal which is asserted low as long
// as a valid clock input is being generated by the
// reader device.
IO_8 input magtrack1 timeout(IO_7) ioCardData;
// This next object allows monitoring of the
// ~Data_valid input signal.
IO_7 input bit ioDataValid;
int read;
unsigned int buffer[78];
. . .
when (io_changes(ioDataValid) to 0) {
read = io_in(ioCardData, buffer);
}
Neurowire Input/Output
The neurowire I/O model implements a full-duplex synchronous transfer of data
to a peripheral device, and is used to transfer data using a fully synchronous
serial data format.
Neurowire I/O is useful for external devices, such as analog-to-digital (A/D) and
digital-to-analog (D/A) converters, and display drivers incorporating serial
interfaces that conform with National Semiconductor’s Microwire™ serial
interface or Motorola's Serial Peripheral Interface (SPI).
Important: The Neurowire I/O model is provided for legacy support. Echelon
recommends using the hardware SPI I/O model instead of the legacy software I/O
model (see
SPI Input/Output on page 107). The hardware SPI interface provides
higher performance with lower software overhead.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to
Series 5000 Neuron Processors and Smart Transceivers.
Hardware Considerations
The neurowire I/O model can operate as the master (drive a clock out) or as the
slave (accept a clock in). In both master and slave modes, up to 255 bits of data
can be transferred at a time. The Neurowire I/O suspends application processing
until the operation is completed.