Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 128)

118 Serial I/O Models
Wiegand Input
The wiegand input model provides an easy interface to any card reader that
supports the Wiegand interface standard.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to
Series 5000 Neuron Processors and Smart Transceivers.
Hardware Considerations
Data from the reader is presented to the Neuron Chip or Smart Transceiver
through two of its first eight I/O pins, IO0 – IO7. Up to four Wiegand devices can
be connected to the Smart Transceiver. Data is read most-significant bit (MSB)
first.
Wiegand data starts as a negative-going pulse on one of the two pins selected.
One input represents a logical 0 bit and the other pin a logical 1 bit, as selected
through the I/O declaration. The bit data on the two lines are mutually
exclusive, and are spaced at least 150 μs apart. Figure 45 on page 119 shows the
timing relationship of the two data lines with respect to each other and to the
Smart Transceiver.
Any unused I/O pin from IO0 to IO7 can be optionally selected as the timeout pin.
When the timeout pin goes high, the function aborts and returns. The
application processor’s watchdog timer is automatically updated during the
operation of this input object.
Incoming data on any of the Wiegand input pins is sampled by a Series 3100
device every 200 ns for a 10 MHz input clock and by a Series 5000 device every
12.5 ns for an 80 MHz system clock (scales inversely with the clock frequency).
Because the Wiegand data is usually asynchronous, care must be taken in the
application program to ensure that this function is called in a timely manner in
order that no incoming data is lost.