Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 66)

56 Parallel I/O Models
• Master and slave A connections are typically used for parallel port
interfaces and for Neuron Chip/Smart Transceiver to Neuron Chip/Smart
Transceiver communication.
• Slave B connections are typically used for communicating from a
microprocessor bus to a Neuron Chip or Smart Transceiver.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to
Series 5000 Neuron Processors and Smart Transceivers.
Hardware Considerations
Pins IO0 – IO10 can be configured as a bidirectional 8-bit data and 3-bit control
port for connecting to an external processor. The other processor can be a
computer, microcontroller, or another Neuron Chip or Smart Transceiver (for
gateway applications). The parallel interface can be configured in master, slave
A, or slave B mode. Typically, two Smart Transceivers interface in master/slave
A mode, and a Smart Transceiver interfaces with a microprocessor in the slave B
configuration, with the other microprocessor as the master. Handshaking is used
in both modes to control the instruction execution, and application processing is
suspended for the duration of the transfer (up to 255 bytes/transfer).
Upon a reset condition, the master processor monitors the low transition of the
handshake (HS) line from the slave, then passes a CMD_RESYNC (0x5A)
command for synchronization. This command must be sent within 0.84 seconds
after reset goes high (for a Series 3100 slave running at 10 MHz or a Series 5000
slave at any clock rate), to avoid a watchdog reset error condition.
The CMD_RESYNC command is followed by the slave acknowledging with a
CMD_ACKSYNC (0x07) command. This synchronization ensures that both
processors are properly reset before data transfer occurs. When interfacing two
Smart Transceivers, these characters are passed automatically. However, when
using parallel I/O to interface the Smart Transceiver to a microprocessor, that
microprocessor must duplicate the interface signals and characters that are
automatically generated by the parallel I/O function of the Smart Transceiver.
For additional information, see the
Parallel I/O Interface to the Neuron Chip
engineering bulletin.
The timing numbers listed in this section are valid for both an explicit I/O call or
an implicit I/O call through a when clause, and are assumed to be for a Series
3100 Smart Transceiver running at 10 MHz.
Master Mode and Slave A Mode
The master mode and the slave A mode are recommended when interfacing two
Neuron Chips or Smart Transceivers. In a master/slave A configuration, the
master drives the IO8 pin as a chip select and the IO9 pin to specify a read or
write cycle, and the slave drives the IO10 pin as a handshake (HS)
acknowledgment (see Figure 19 on page 57).
Important: The HS line should be pulled up (inactive) with a 10 kΩ resistor to
ensure proper resynchronization behavior after the slave device resets.