Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 166)

156 Timer/Counter Output Models
Edgedivide Output
The edgedivide I/O model is used to control an output pin by toggling its logic
state every output_value negative edges on an input pin. This toggling results in
a acts as a frequency divider by providing an output frequency on either pin IO0
or IO1: divide-by-n*2 counter, where n is the value defined by the output_value
argument.
The output frequency is a divided-down version of the input frequency applied on
pins IO4 – IO7. This object is useful for any divide-by-n operation, where n is
passed to the timer/counter object through the application program and can be
from 1 to 65 535. The value of 0 forces the output to the off level and halts the
timer/counter.
This model applies to Series 3100 Neuron Chips and Smart Transceivers, and to
Series 5000 Neuron Processors and Smart Transceivers.
Hardware Considerations
A new divide value does not take effect until after the output toggles, with two
exceptions:
• If the output is initially disabled, the new (non-zero) output starts
immediately after t
fout
• For a new divide value of 0, the output is disabled immediately
Normally, the negative edges of the input sync pulses are the active edge. Using
the invert keyword in the object declaration makes the positive edge active.
The initial state of the output pin is logic 0 by default. This initial state can also
be changed to logic 1 through the object declaration.
Figure 58 on page 157 shows the pinout and timing information for this output
model.