Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 125)

I/O Model Reference 115
select(IO_7)
Set this option to have pin IO_7 used as a slave select (SS) signal in slave
mode. In slave mode, this option is used when there are multiple slaves
connected to a master. However, when the device is the only slave (and thus
there is no need for the master to use a dedicated slave select signal), then
pin IO_7 should be separately declared as an input pin and externally
grounded.
In master mode, the select keyword is not used; thus, IO_7 can be used for
other purposes.
clock( const-expr )
The clock selection can be an integer from 0 to 7, and selects a clock divisor
for the SPI interface. This clock divisor and the input clock control the serial
bit rate of the SPI interface. Clock selection applies only to master mode.
For a Series 3100 or Series 5000 device at 10 MHz, the minimum serial bit
rate is 19531 bps and the maximum rate is 156250 bps.
If you omit this keyword, the default used is clock(0).
invert
By default, the clock is idle at 1. Set this option to specify that the clock is
idle at 0.
This definition relates directly to the clock polarity (CPOL) parameter
defined for other SPI implementations. Using the invert keyword is
equivalent to defining CPOL = 0; the default declaration is equivalent to
defining CPOL =1. Both the SPI master and the SPI slave are required to
use the same clock polarity.
See Hardware Considerations on page 107 for more information.
clockedge(+|-)
Set this option to + for in-phase interfaces (CPHA=1) to specify that data is
valid on the rising edge of the clock. Set this option to – for out-of-phase
interfaces (CPHA=0) to specify that data is valid on the falling edge of the
clock. By default, if you omit this parameter, data is valid on the rising edge
of the clock (clockedge(+)). The clock phase (CPHA) must be identically
specified for both the SPI master and SPI slave devices.
In-phase interfaces present the data bit on the first transition of the clock
signal, and latch it on the second transition. Out-of-phase interfaces present
the data bit before the first transition of the clock signal, and latch it on the
first transition.
See
Hardware Considerations on page 107 for more information.
neurowire
Set this option to select Neurowire compatible mode, where the MOSI and
MISO pins do not change direction based on any slave select. The default is
SPI mode.
io-object-name
Specifies a name for the I/O object, in the ANSI C format for variable
identifiers.