Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 109)

I/O Model Reference 99
communication interface that is compatible with EIA-232 serial interfaces (with
the exception of voltage levels). External driver hardware can be used to adjust
the voltage levels. The SCI I/O model uses the UART hardware and interrupt
capability in designated Neuron Chips and Smart Transceivers. You cannot use
both hardware SCI and hardware SPI I/O in the same application.
The hardware SCI I/O object does not include any form of hardware flow control,
such as CTS/RTS flow control. If your application requires flow control, you must
implement some form of handshaking in your application.
This model applies to 3120 Power Line Smart Transceivers, 3150 Power Line
Smart Transceivers, 3170 Power Line Smart Transceivers, Series 5000 Neuron
Processors and Smart Transceivers.
Hardware Considerations
Pins IO8 and IO10 can be configured as asynchronous SCI input and output
lines, respectively. The SCI object model supports the following bit rates for half-
duplex transfers: 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, and
115200 bits per second. The effective transmitted data rate for half-duplex
transfers corresponds to the bit rate at all speeds. There are no inter-byte idle
periods, and the bit rate for the input and output can not be independently
specified.
For full-duplex transfers, when data is being received and transmitted at the
same time, the effective bit rate will be 60% at 57600 bits per second, and 30% at
115200 bits per second. All other bit rates specified above for half-duplex
transfers are also supported for full-duplex transfers. No errors are introduced
(other than inter-byte spacing of transmitted data) under these conditions.
For 6.5536 MHz operation (Series 3100 power line Smart Transceivers), the bit
rates are limited to a maximum of 19200 bits per second for both half and full-
duplex transfers.
The frame format is one start bit, eight data bits, and one stop bit plus a parity
bit or two stop bits. Up to 255 output bytes and 255 input bytes can be
transferred at a time. If an input stop bit has the wrong polarity, the interface
attempts to recover and re-synchronize. However, a framing error is flagged in
the status register. If necessary, the application code can use other bit I/O pins
for flow-control handshaking.
This I/O model depends on interrupts to receive data at high speed. After
reception has been set up, control is returned to the application immediately, and
the application needs to poll the I/O model for reception completion. Reception
can be suspended and resumed by disabling and enabling interrupts. Turning off
interrupts might be required when going off-line, or for ensuring that other time-
critical application execution is not disturbed by background interrupts.
Additionally, SCI reception can also be aborted. Note that for Series 3100
devices, sustained reception at 115200 bps can starve the application processor.
Care must be given to allow the Smart Transceiver to process received bytes in a
timely manner and update the watchdog timer.
However, data transmission is
not handled by interrupts; control is returned to
the application only after the last byte has been placed in the transmission shift
register. It is important to note that if previously set up, reception interrupts
work even while transmission is taking place, thus providing the full duplex
interface.