Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 73)

I/O Model Reference 63
unsigned int buffer[MAX_IN];
} inData;
unsigned int i;
when (reset) {
outData.length = OUT_LEN; // assign output length
for(i=0; i<OUT_LEN; ++i) // fill output buffer with 1s
outData.buffer[i]=i+1;
}
when (io_out_ready(parallelBus)) {
io_out(parallelBus, &outData); // output buffer
}
when (io_in_ready(parallelBus)) {
// declare the maximum input buffer acceptable
inData.length = MAX_IN;
io_in(parallelBus, &inData); // store input in buffer
io_out_request(parallelBus); // request to output buffer
}
Slave B Mode
The slave B mode is recommended for interfacing a Smart Transceiver acting as
the slave to a microprocessor acting as the master. When configured in slave B
mode, the Smart Transceiver accepts the IO8 signal as a chip select and the IO9
signal to specify whether the master will read or write, and accepts the IO10
signal as a register select input. Series 5000 devices accept the IO11 pin as an
interrupt request signal. When the CS~ pin is asserted and either IO10 is low or
IO10 is high and R/W~ is low, pins IO0 – IO7 form the bidirectional data bus.
When IO10 is high, R/W~ is high, and CS~ is asserted, IO0 is driven as the HS
acknowledgment signal to the master.
The Smart Transceiver can appear as two registers in the master’s address space:
• A read/write data register
• A read-only status register
Therefore, reads by the master to an odd address access the status register for
handshaking acknowledgments, and all other reads or writes access the data
register for I/O transfers. The least-significant bit (LSB) of the control register,
which is read through pin IO0, is the HS bit. The master reads the HS bit after
every master read or write.
Important: The D0/HS line should be pulled up (inactive) with a 10 kΩ resistor
to ensure proper resynchronization behavior after resets.
When acting as a slave to a microprocessor, the Smart Transceiver slave B mode
handles all handshaking and token passing automatically. However, the master
microprocessor must read the HS bit after each transaction and must also
internally track the token passing. This mode is designed for use with a master
processor that uses memory-mapped I/O, because the LSB of the master’s
address bus is typically connected to the IO10 pin of the Smart Transceiver. This
is illustrated in Figure 22 and Figure 23 on page 64.