Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 41)

I/O Model Reference 31
2
Direct I/O Models
This chapter describes direct input/output models. Direct I/O models
are based on a logic level at the I/O pins; none of the Neuron Chip or
Smart Transceiver hardware’s timer/counters are used in conjunction
with these I/O objects. These models can be used in multiple,
overlapping combinations within the same Neuron Chip or Smart
Transceiver.