Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 70)

60 Parallel I/O Models
Table 22. Slave A Mode Parallel I/O Latency Values for Series 3100 Devices
Symbol Description Minimum Typical Maximum
t
sarws
R/W~ setup before falling edge of CS~ 25 ns — —
t
sarwh
R/W~ hold after rising edge of CS~ 0 ns — —
t
sacspw
CS~ pulse width 45 ns — —
t
sahsh
HS hold after rising edge of CS~ 0 ns — —
t
sahsv
HS valid after rising edge of CS~ — — 50 ns
t
sawdd
Slave A drive of DATA after rising edge of
R/W~ (Notes 1, 2) 0 ns 5 ns —
t
sawds
Write data valid before falling edge of HS
(Note 3) 150 ns 2 XIN —
t
sawdh
Write data valid after rising edge of CS~
(Note 3) 150 ns
(Note 4) 2 XIN —
t
sardz
Slave A three-state DATA after falling edge
of R/W~ (Note 1) — — 50 ns
t
sards
Read data setup before rising edge of CS~ 25 ns — —
t
sardh
Read data hold after rising edge of CS~ 10 ns — —
Notes:
1. Refer to the appropriate Neuron Chip or Smart Transceiver data sheet for detailed
measurement information.
2. For Smart Transceiver-to-Smart Transceiver operation, bus contention (t
mrdz
, t
sawdd
) is
eliminated by firmware, ensuring that a zero state is present when the token is
passed between the master and slave. See the
Parallel I/O Interface to the Neuron
Chip engineering bulletin for additional information.
3. XIN represents the period of the Smart Transceiver input clock (100 ns for a Series
3100 device at 10 MHz), or the period of the system clock for a Series 5000 device
(12.5 ns at 80 MHz).
4. If t
sarwh
< 150 ns, then t
sawdh
= t
sarwh
.
5. In slave A mode, the HS signal is high a minimum of 4 XIN periods. The typical time
HS is high during consecutive data reads or consecutive data writes is also 4 XIN
periods.
Example
This section describes a pair of example programs that transfer data in a parallel
I/O master/slave A configuration. The code assumes two devices hardwired as
shown in Figure 19 on page 57. The master program writes the test_data to the