Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 65)

I/O Model Reference 55
A user-specified name for the I/O object, in the ANSI C format for variable
identifiers.
Usage
unsigned int data-byte ;
data-byte = io_in( io-object-name , address );
data-byte = io_in( io-object-name );
io_out( io-object-name , address , data-byte );
io_out( io-object-name , data-byte );
Example
IO_0 muxbus ioMuxBus;
when (. . .) {
// Write two bytes to addresses 0x20 and 0x21,
// and wait for the data at 0x20 to contain
// the 0x80 value.
io_out(ioMuxBus, 0x20, 128);
io_out(ioMuxBus, 0x21, 1);
if ((io_in(ioMuxBus, 0x20) & 0x80) == 0) {
// Continue to read the same address.
while ((io_in(ioMuxBus) & 0x80) == 0);
}
}
Parallel Input/Output
The parallel I/O model uses eleven I/O pins for an 8 bit parallel interface with
handshaking. This interface allows data transfer at rates up to 3.3 Mbps. A
parallel interface can be used for the following applications:
• To interface a Neuron Chip or Smart Transceiver to an attached
microprocessor or to the bus of a computer system. This interface can use
the Neuron Chip or Smart Transceiver as a communications chip with an
existing processor-based system, provide more application performance,
or supply more memory. This type of interface is enhanced with the
Microprocessor Interface Program (MIP; with a parallel or dual-ported
RAM interface). The MIP moves network variable and application
message processing to the attached processor.
• For application-level gateways, two Neuron Chips or Smart Transceivers
(or one of each) might be connected back to back across the parallel
interface, producing two transceiver interfaces to transport data from one
system to the other.
This interface is bidirectional, with the direction (read/write) controlled by the
device that is declared as the master. When using this interface, the Neuron
Chip or Smart Transceiver can be either a master or a slave. The parallel I/O
model provides three different configurations of the parallel I/O interface: master,
slave A, and slave B: