Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 148)

138 Timer/Counter Input Models
MHz, and the timer/counter clock is clock (7). This yields a 25.6 μs timer/counter
clock resolution.
The max-period parameter is set to cause an overflow at 110% of the start cycle
(the timer/counter will count up from this value):
65149
10 * 6 . 25
) 10 * 9 ( * 10 . 1
65536
6
3
=
⎟⎟
⎠
⎞
⎜⎜
⎝
⎛
−
−
−
Given the one and zero data periods, the threshold value is:
65215
66 65149
10 * 6 . 25
2
) 10 * 25 . 2 ( ) 10 * 125 . 1 (
65149
6
3 3
=
+ =
⎟
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎜
⎝
⎛
⎥
⎦
⎤
⎢
⎣
⎡ +
+
−
− −
This encoder always sends 32 bits, so the count will be 32, and the returned
input-buffer will be an array of 4 bytes.
// This is the demodulated IR input.
// Use the non-inverted mode to read falling to falling
// input periods.
IO_4 input infrared ded clock (7) ioIr;
// This object allows the application to monitor the input
// signal before entering the io_in() function.
IO_4 input bit ioIrLevel;
unsigned int bits;
unsigned int irb[4];
. . .
when (io_changes(ioIrLevel) to 0) {
bits = io_in(ioIr, irb, 32, 65149UL, 65149UL + 66UL);
if (bits == 32) {
// So far, a valid data message.
. . .
}
}
Ontime Input
For a Series 3100 device, the ontime I/O model measures pulsewidth or period of
an input signal (the high or low period) in units of the clock period:
time_on (ns) = return_value * 2000 * 2^(clock) / input clock (MHz)
where clock ranges from 0..7
For a Series 5000 device, the ontime I/O model measures pulsewidth or period of
an input signal (the high or low period) in units of the clock period: