Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 191)

I/O Model Reference 181
equivalent of an OFF state. When using the level output configuration, there is
always some amount of output signal; use an output value that is about 95% of
the half-cycle period to approximate the OFF state.
Syntax
pin [output] triac [pulse] sync ( pin-nbr ) [invert] [clock ( const-expr )]
[clockedge (+)|(-)|(+-)] io-object-name ;
pin
An I/O pin. Triac output can specify pins IO_0 or IO_1. If IO_0 is specified,
the sync pin can be IO_4 through IO_7. If IO_1 is specified, the sync pin
must be IO_4.
sync ( pin-nbr )
Specifies the sync pin, which is the input trigger signal.
invert
Causes the output signal to be inverted, normally high. The default output
signal is normally low.
clock ( const-expr )
Specifies a clock in the range 0 to 7, where 0 represents the fastest clock and
7 represents the slowest clock. The default value is clock 0.
You can change resolution for the timer base clock frequency by calling the
io_set_clock( ) function with a clock value in the range 0..7 (using one of the
TCCLK_* macros defined in <echelon.h>). This function overrides the
resolution value specified for clock() within the I/O object declaration.
For an application running on a Series 5000 device, you can specify an
increased resolution for the timer base clock frequency by calling the
io_set_clock() function with a clock value in the range 0..15 (using one of the
TCCLK_* macros defined in <echelon.h>). This function overrides the
resolution value specified for clock() within the I/O object declaration.
See Appendix A, Timer/Counter Periods and Resolution , on page 187, for a
description of the timer resolution and maximum range for each specification
of the clock() value or each value of the TCCLK_* macros. See the Neuron C
Reference Guide for information about the io_set_clock() function.
clockedge (+)|(-)|(+-)
(+) Causes the sync input to be positive-edge sensitive.
(-) Causes the sync input to be negative-edge sensitive. This is the default.
(+-) Causes the sync input to be both positive- and negative-edge sensitive
(valid for all Neuron 3120xx Chips, all models of Neuron 3150 Chips except
minor model 0, all Smart Transceivers, and Series 5000 devices). Can be
used with pulse mode only.
Note: The clockedge (+-) option does not work with minor model 0 of Neuron
3150 Chips. When using a Neuron 3150 Chip, a 3150 Smart Transceiver, or
a LonBuilder emulator, the compiler inserts code in the application that