Echelon I/O Model Reference for Smart Transceivers and Neuron Chips - Manual (Page 107)

I/O Model Reference 97
This pragma must appear prior to the use of any I/O function, such as io_in( ) or
io_out( ).
For examples on the use of the Neurowire input/output model, see the following
engineering bulletins: Driving a Seven Segment Display with the Neuron Chip
(part no. 005-0014-01) and Analog-to-Digital Conversion with the Neuron Chip
(part no. 005-0019-01).
Syntax
IO_8 neurowire master | slave [select ( pin-nbr )] [timeout ( pin-nbr )]
[kbaud ( const-expr )] [clockedge (+|-)] io-object-name ;
IO_8
Specifies pin IO_8. The Neurowire object requires pins IO_8 through IO_10
and must specify IO_8. The select pin must be one of IO_0 through IO_7.
Pin IO_8 is the clock, driven by the Neuron Chip or Smart Transceiver (or the
external master). Pin IO_9 is serial data output and IO_10 is serial data
input. Up to 255 bits of data can be transferred at a time.
master
Specifies that the Neuron Chip or Smart Transceiver provides the clock on
pin IO_8, which is configured as an output pin.
slave
Specifies that the Neuron Chip or Smart Transceiver senses the clock on pin
IO_8, which is configured as an input pin. The maximum input clock rate is
72 kbps, 50/50 duty cycle, for a Series 3100 device with a 40 MHz input clock.
This rate scales proportionally to the input clock.
select ( pin-nbr )
Specifies the chip select pin for a Neurowire master. This keyword is
applicable to master mode only.
Before the data transfer, the chip select pin goes low; after the data transfer,
the select pin goes high. In addition to this declaration with the select
keyword, the chip select pin must also be declared with a bit output object,
unless there is no chip select pin in use. If no chip select pin is in use, the pin
declared as the select pin can also be declared as any of the allowable input
objects for that pin (for example, bit input).
timeout ( pin-nbr )
Specifies the optional timeout signal pin for a Neurowire slave, in the range
of IO_0 to IO_7. This keyword is applicable to slave mode only.
When a timeout signal pin is used, the Neuron firmware checks the logic
level at this pin whenever it is waiting for either rising or falling edges of the
clock. If a logic level of 1 is sensed, the transfer is terminated. This allows
the use of an external timeout signal, or an internally generated timeout
signal, such as an inverted oneshot output object, to limit the duration of the
transfer. The watchdog timer is updated by this object with every falling
edge of the clock on pin IO_8.