Altera Transceiver PHY IP Core - Manual (Page 273)

Example 11-1: For RE
RX _latency_ RE = <R X P CS latency in parallel clock cycles >
+ (<RX PMA latency in UI >
+ <
TX_latency_RE = <TX PCS latency in parallel clock cycles>
+ <T X PMA latency in U I > Tx bitslip latency > +
rx_std_bitslipboundaryselect > delay )
Note:
In single width (PMA =10) mode, add one UI delay per value of
rx_std_bitslipboundaryselect
. For
constant round-trip delay (RX+TX), set
tx_std_bitslipboundaryselect
<= (5'd9 -
rx_std_bitslip-
boundaryselect
).
In double width (PMA =20) mode, add one UI delay per value of (5'd9 -
rx_std_bitslipboundaryse-
lect
). For constant round-trip delay (RX+TX), set
tx_std_bitslipboundaryselect
<=
rx_std_bitslipboundaryselect
.
Example 11-2: For REC
For REC
= <RX PCS latency in parallel clock cycles>
+ <RX PMA latency in UI> + <rx_clkout phase shift of tx_clkout>
TX_latency_REC = <TX PCS latency in parallel clock cycles>
+ <TX PMA latency in UI>
RX_latency_REC
Example 11-3: For Round Trip Delay
Launch_time (from TX pins) =<clock arrival time> + <data arrival time>
= <clock arr ival time>
+ <TX latency in R E C> (tx bits lip=0 )
= <t
PD
G P L L to CM U P L L - t
feedback
>
+ ((<TX _latency in REC > × <tx_clkout_period >)
+ t
TX_tc lock_output
)
=<latency time in RE > - <R X latency time in REC >
= (<Round_trip _latency > × <tx_clkout_period >)
– ((<RX _latency in RE C > × <rx_clkout_period >)
+ <t
PDI O >R X_ deser
>
+ <rx_c lkout_phase_WRT_tx_clkout/360 × rx _clkout_period> )
Arrival_time (at RX pins)
Total Delay = <Arrival_time> - <Launch_time>
UG-01080
2015.01.19
Deterministic Latency PHY Delay Estimation Logic 11-5
Deterministic Latency PHY IP Core Altera Corporation
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