Altera Transceiver PHY IP Core - Manual (Page 560)

Example 16-8: Register-Based Write of Logical Channel 0 V
OD
Setting
System Console is used for the following settings:
#Setting logical channel 0
write_32 0x8 0x0
#Setting offset to VOD
write_32 0xB 0x0
#Setting data register to 40
write_32 0xC 0x28
#Writing all data
write_32 0xA 0x1
Ā
Register-Based Read
Complete the following steps, using a state machine as an example, for a read:
1. Read the
control and status
register
busy
bit (bit 8) until it is clear.
2. Write the logical channel number of the channel to be read to the
logical channel number
register.
3. Write the <feature> offset address.
4. Write the
control and status
register
read
bit to 1’b1.
5. Read the
control and status
register
busy
bit. Continue to read the busy until the value is zero.
6. Read the
data
register to get the data.
Example 16-9: Register-Based Read of Logical Channel 2 Pre-Emphasis Pretap Setting
System Console is used for the following settings:
#Setting logical channel 2
write_32 0x8 0x2
#Setting offset to pre-emphasis pretap
write_32 0xB 0x1
#Writing the logical channel and offset for pre-emphasis pretap
write_32 0xA 0x2
#Reading data register for the pre-emphasis pretap value
read_32 0xC
Changing Transceiver Settings Using Streamer-Based Reconfiguration
The Streamer’s registers allow you to change to the PCS datapath settings, clock settings, PRBS settings,
and PLL parameters by reading the new settings from an on- or off-chip ROM.
Streamer Module Registers lists the Streamer’s memory-mapped registers that you can access using
Avalon-MM read and write commands on reconfiguration management interface.
The following sections show how to change transceiver settings using Streamer modes 0 and 1.
UG-01080
2015.01.19
Register-Based Read 16-43
Transceiver Reconfiguration Controller IP Core Overview Altera Corporation
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