Altera Transceiver PHY IP Core - Manual (Page 495)

Parameter Range Description
Enable rx_std_pcfifo_full port On/Off When you turn this option On, the RX Phase
compensation FIFO outputs a FIFO full status
flag.
Enable rx_std_pcfifo_empty port On/Off When you turn this option On, the RX Phase
compensation FIFO outputs a FIFO empty
status flag.
Enable rx_std_rmfifo_empty port On/Off When you turn this option On, the rate match
FIFO outputs a FIFO empty status flag. The
rate match FIFO compensates for small clock
frequency differences between the upstream
transmitter and the local receiver clocks by
inserting or removing skip (SKP) symbols or
ordered sets from the interpacket gap (IPG) or
idle stream.
Enable rx_std_rmfifo_full port On/Off When you turn this option On, the rate match
FIFO outputs a FIFO full status flag.
Related Information
Transceiver Architecture in Cyclone V Devices
Byte Ordering Block Parameters
The RX byte ordering block realigns the data coming from the byte deserializer. This block is necessary
when the PCS to FPGA fabric interface width is greater than the PCS datapath.
Because the timing of the RX PCS reset logic is indeterminate, the byte ordering at the output of the byte
deserializer may or may not match the original byte ordering of the transmitted data.
Note: For more information refer to the Byte Ordering section in the Transceiver Architecture in
Cyclone V Devices.
Table 15-9: Byte Ordering Block Parameters
Parameter Range Description
Enable RX byte ordering On/Off When you turn this option On, the PCS includes the
byte ordering block.
Byte ordering control
mode
manual
auto Specifies the control mode for the byte ordering block.
The following modes are available:
• Manual: Allows you to control the byte ordering
block
• Auto: The word aligner automatically controls the
byte ordering block once word alignment is achieved.
15-12 Byte Ordering Block Parameters
UG-01080
2015.01.19
Altera Corporation Cyclone V Transceiver Native PHY IP Core Overview
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