Altera Transceiver PHY IP Core User Manual
Page 448
zation process again. Lock status is available to the FPGA fabric. The following table describes the
Interlaken frame synchronizer parameters.
Table 14-27: Interlaken Frame Synchronizer Parameters
Parameter
Range
Description
teng_tx_framsync_enable
On/Off
When you turn this option On, the 10G
PCS frame generator is enabled.
Enable rx_10g_frame port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_frame
output
port. This signal is asserted to indicate
the beginning of a new metaframe
inside.
Enable rx_10g_frame_lock_port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_frame_lock
output port. This signal is asserted to
indicate that the frame synchronization
state machine has achieved frame lock.
Enable rx_10g_frame_mfrm_err port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_frame_mfrm_
err
output port. This signal is asserted
to indicate an metaframe error.
Enable rx_10g_frame_sync_err port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_frame_sync_
err
output port. This signal is asserted
to indicate synchronization control
word errors. This signal remains
asserted during the loss of block_lock
and does not update until block_lock is
recovered.
Enable rx_10g_frame_skip_ins port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_frame_skip_
ins
output port. This signal is asserted
to indicate a SKIP word was received by
the frame sync in a non-SKIP word
location within the metaframe.
Enable rx_10g_frame_pyld_ins port
On/Off
When you turn this option On, the 10G
PCS includes the
rx_10g_frame_pyld_
ins
output port. This signal is asserted
to indicate a SKIP word was not
received by the frame sync in a SKIP
word location within the metaframe.
UG-01080
2015.01.19
10G PCS Parameters for Arria V GZ Native PHY
14-37
Arria V GZ Transceiver Native PHY IP Core
Altera Corporation