Altera Transceiver PHY IP Core - Manual (Page 399)

Table 13-19: Native PHY Common Interfaces
Name Direction Description
Clock Inputs and Output Signals
tx_pll_refclk[<r>-1:0] Input The reference clock input to the TX PLL.
tx_pma_clkout[<n>-1:0] Output TX parallel clock output from PMA.
This clock is only available in PMA
direct mode.
rx_pma_clkout[<n>-1:0] Output RX parallel clock (recovered clock)
output from PMA
rx_cdr_refclk[<n>-1:0] Input Input reference clock for the RX PFD
circuit.
ext_pll_clk[ <p> -1:0] Input This optional signal is created when you
select the Use external TX PLL option. If
you instantiate a fractional PLL which is
external to the Native PHY IP, then
connect the output clock of this PLL to
ext_pll_clk
.
Resets
pll_powerdown[<p>-1:0] Input
When asserted, resets the TX PLL. Active
high, edge sensitive reset signal. By
default, the Arria V Native Transceiver
PHY IP Core creates a separate
pll_
powerdown
signal for each logical PLL.
However, the Fitter may merge the PLLs
if they are in the same transceiver bank.
PLLs can only be merged if their
pll_
powerdown
signals are driven from the
same source. If the PLLs are in separate
transceiver banks, you can choose to
drive the
pll_powerdown
signals
separately.
13-24 Common Interface Ports
UG-01080
2015.01.19
Altera Corporation Arria V Transceiver Native PHY IP Core
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