Altera Transceiver PHY IP Core User Manual
Page 348
Name
Direction
Description
tx_pma_qpipullup
Input
Control input port for Quick Path Intercon‐
nect (QPI) applications. When asserted, the
transmitted pulls the output signal to high
state. Use this port only for QPI applica‐
tions.
tx_pma_qpipulldn
Input
Control input port for Quick Path Intercon‐
nect (QPI) applications. This is an active
high signal. When asserted, the transmitter
pulls the output signal in low state. Use this
port only for QPI applications.
tx_pma_txdetectrx
Input
When asserted, the RX detect block in the
TX PMA detects the presence of a receiver
at the other end of the channel. After
receiving a
tx_pma_txdetectrx
request, the
receiver detect block initiates the detection
process. Only for QPI applications.
tx_pma_rxfound
Output
Indicates the status of an RX detection in
the TX PMA. Only for QPI applications.
rx_pma_qpipulldn
Input
Control input port for Quick Path Intercon‐
nect (QPI) applications. This is an active
high signal. When asserted, the receiver
pulls the input signal in low state. Use this
port only for QPI applications.
TX and RX Serial Ports
tx_serial_data[ <n> -1:0]
Output
TX differential serial output data.
rx_serial_data[ <n> -1:0]
Input
RX differential serial output data.
Control and Status Ports
rx_seriallpbken[ <n> -1:0]
Input
When asserted, the transceiver enters
loopback mode. Loopback drives TX data to
the RX interface.
rx_set_locktodata[ <n> -1:0]
Input
When asserted, programs the RX CDR to
manual lock to data mode in which you
control the reset sequence using the
rx_
setlocktoref
and
rx_setlocktodata
.
Refer to Reset Sequence for CDR in Manual
Lock Mode in Transceiver Reset Control in
Stratix V Devices for more information
about manual control of the reset sequence.
12-50
Common Interface Ports for Stratix V Native PHY
UG-01080
2015.01.19
Altera Corporation
Stratix V Transceiver Native PHY IP Core