Altera Transceiver PHY IP Core - Manual (Page 46)

Figure 3-9: Stratix IV Clock Generation and Distribution
pll_ref_clk
644.53125 MHz
10.3125
Gbps serial
516.625
MHz
257.8125
MHz
516.625
MHz
257.8125
MHz
156.25 MHz
10GBASE-R Transceiver Channel - Stratix IV GT
TX
RX
TX PCS
(hard IP)
TX PCS
(soft IP)
20 40 64-bit data, 8-bit control
64-bit data, 8-bit control
TX PMA
/2
10.3125
Gbps serial
RX PCS
(hard IP)
RX PCS
(soft IP)
20 40
RX PMA
/2
5/4
TX PLL
8/33
GPLL
xgmii_rx_clk
xgmii_tx_clk
Related Information
Reset Control and Power Down
10GBASE-R PHY Clocks for Stratix V Devices
The following figure illustrates clock generation and distribution in Stratix V devices.
3-22 10GBASE-R PHY Clocks for Stratix V Devices
UG-01080
2015.01.19
Altera Corporation 10GBASE-R PHY IP Core
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