Altera Transceiver PHY IP Core - Manual (Page 345)

Figure 12-5: Stratix V Native PHY Common Interfaces
tx_pll_refclk[<r>-1:0]
tx_pma_clkout[<n>-1:0]
rx_pma_clkout[<n>-1:0]
rx_cdr_refclk[<r>-1:0]
Clock Input
& Output Signals
rx_seriallpbken[<n>-1:0]
rx_setlocktodata[<n>-1:0]
rx_setlocktoref[<n>-1:0]
pll_locked[<p>-1:0]
rx_is_lockedtodata[<n>-1:0]
rx_is_lockedtoref[<n>-1:0]
rx_clkslip[<n>-1:0]
Control &
Status Ports pll_powerdown[<p>-1:0]
tx_analogreset[<n>-1:0]
tx_digitalreset[<n>-1:0]
rx_analogreset[<n>-1:0]
rx_digitalreset[<n>-1:0]
Resets
QPI
tx_pma_parallel_data[<n>80-1:0]
rx_pma_parallel_data[<n>80-1:0]
tx_parallel_data[<n>64-1:0]
rx_parallel_data[<n>64-1:0]
tx_pma_qpipullup
tx_pma_qpipulldn
tx_pma_txdetectrx
tx_pma_rxfound
rx_pma_qpipulldn
Parallel
Data Ports
tx_serial_data[<n>-1:0]
rx_serial_data[<n>-1:0]
TX & RX
Serial Ports
reconfig_to_xcvr [(<n>70-1):0]
reconfig_from_xcvr [(<n>46-1):0]
tx_cal_busy[<n>-1:0]
rx_cal_busy[<n>-1:0]
Reconfiguration
Interface Ports
Native PHY Common Interfaces
ext_pll_clk[<p>-1:0]
Table 12-38: Native PHY Common Interfaces
Name Direction Description
Clock Inputs and Output Signals
tx_pll_refclk[ <r> -1:0]
Input The reference clock input to the TX PLL.
tx_pma_clkout[ <n> -1:0]
Output TX parallel clock output from PMA
rx_pma_clkout[ <n> -1:0]
Output RX parallel clock (recovered clock) output
from PMA
rx_cdr_refclk[ <n> -1:0]
Input Input reference clock for the RX PFD
circuit.
ext_pll_clk[ <p> -1:0]
Input This optional signal is created when you
select the Use external TX PLL option. If
you instantiate a fractional PLL which is
external to the Native PHY IP, then connect
the output clock of this PLL to
ext_pll_
clk
.
Resets
UG-01080
2015.01.19
Common Interface Ports for Stratix V Native PHY 12-47
Stratix V Transceiver Native PHY IP Core Altera Corporation
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