Altera Transceiver PHY IP Core User Manual
Page 416
Name
Range
Description
Bonding mode
Non-bonded or x1
Bonded or ×6/xN
fb_compensation
In Non-bonded or x1 mode, each channel is paired
with a PLL.
If one PLL drives multiple channels, PLL merging is
required. During compilation, the Quartus II Fitter,
merges all the PLLs that meet PLL merging require‐
on page 16-57 to
observe PLL merging rules.
Select ×6 to use the same clock source for up to 6
channels in a single transceiver bank, resulting in
reduced clock skew. You must use contiguous
channels when you select ×6 bonding. In addition,
you must place logical channel 0 in either physical
channel 1 or 4. Physical channels 1 and 4 are indirect
drivers of the ×6 clock network.
Select fb_compensation (feedback compensation) to
use the same clock source for multiple channels
across different transceiver banks to reduce clock
skew. For more information about bonding, refer to
"Bonded Channel Configurations Using the PLL
Feedback Compensation Path" in Transceiver
Clocking in Arria V devices chapter of the Arria V
Device Handbook.
Enable simplified data
interface
On/Off
When you turn this option On, the Native PHY
presents only the relevant data bits. When you turn
this option Off, the Native PHY presents the full raw
interface to the fabric. If you plan to dynamically
reconfigure the Native PHY, you must turn this
option Off and you need to understand the mapping
of data to the FPGA fabric. Refer to
more information. When you turn this option On ,
the Native PHY presents an interface that includes
only the data necessary for the single configuration
specified.
Related Information
UG-01080
2015.01.19
General Parameters for Arria V GZ Native PHY
14-5
Arria V GZ Transceiver Native PHY IP Core
Altera Corporation