Altera Transceiver PHY IP Core - Manual (Page 301)

Performance and Resource Utilization for Stratix V Native PHY
This section describes the performance resource utilization for Stratix V native PHY.
Because the 10G PCS, Standard PCS, and PMA are implemented in hard logic, the Stratix V Native PHY
IP Core uses less than 1% of the available ALMs, memory, primary and secondary logic registers.
Parameter Presets
Presets allow you to specify a group of parameters to implement a particular protocol or application.
If you apply a preset, the parameters with specific required values are set for you. When applied, the preset
is in boldface and remains as such unless you change some of the preset parameters. Selecting a preset
does not prevent you from changing any parameter to meet the requirements of your design. The
following figure illustrates the Preset panel and form to create custom presets.
Figure 12-2: Preset Panel and Form To Create Custom Presets
UG-01080
2015.01.19
Performance and Resource Utilization for Stratix V Native PHY 12-3
Stratix V Transceiver Native PHY IP Core Altera Corporation
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