Altera Transceiver PHY IP Core - Manual (Page 624)

Description
Static control for the continuous time equalizer in the receiver buffer. The equalizer has 3 settings from 0–
2 corresponding to the increasing AC gain.
Options
0-2
Assign To
Pin - RX serial data
XCVR_RX_COMMON_MODE_VOLTAGE
Pin Planner and Assignment Editor Name
Receiver Buffer Common Mode Voltage
Description
Receiver buffer common-mode voltage.
Note: Contact Altera for using this assignment.
Related Information
How to Contact Altera on page 21-42
XCVR_RX_SD_ENABLE
Pin Planner and Assignment Editor Name
Receiver Signal Detection Unit Enable/Disable
Description
Enables or disables the receiver signal detection unit. During normal operation
NORMAL_SD_ON=FALSE
,
otherwise
POWER_DOWN_SD=TRUE
.
Used for the PCIe PIPE PHY, SATA and SAS protocols.
Options
FALSE
TRUE
Assign To
Pin - RX serial data
XCVR_RX_SD_OFF
Pin Planner and Assignment Editor Name
Receiver Cycle Count Before Signal Detect Block Declares Loss Of Signal
19-30 XCVR_RX_COMMON_MODE_VOLTAGE
UG-01080
2015.01.19
Altera Corporation Analog Parameters Set Using QSF Assignments
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