Altera Transceiver PHY IP Core User Manual
Page 541
1. Read the DFE
control and status
register busy bit (bit 8) until it is clear.
2. Write the logical channel number of the channel to be updated to the DFE
logical channel
number
register.
3. Write the
DFE_offset
address of 0x0 (DFE control register).
4. Write the data value 2'b10 to the data register to enable DFE power.
This powers up the DFE and DFE adaptation engine is disabled.
5. Write the
control and status
register write bit to 1'b1.
6. Read the DFE
control and status
register busy bit (bit 8) until it is clear.
7. Write the
DFE_offset
address of 0x1 (DFE Tap 1 register).
8. Write the
data
value 3'b101 to the data register.
9. Write the
control and status
register write bit to 1'b1.
10.Read the
control and status
register busy bit. Continue to read the
busy
bit while its value is 1‘b1.
11.When
busy
equals 1b’0, the Transceiver Reconfiguration Controller has updated the logical channel.
The register-based write to use DFE in manual mode and set the first DFE tap value to 5 for logical
channel 0 as shown in the following example:
Example 16-3: Register-Based Write To Use DFE in Manual Mode and Set the First DFE Tap
Value to 5 for Logical Channel 0
#Setting logical channel 0
write_32 0x18 0x0
#Setting DFE offset to 0x0
write_32 0x1B 0x0
#Setting data register to 2
write_32 0x1C 0x2
#Writing the data to use DFE in Manual mode
write_32 0x1A 0x1
#Setting DFE offset to 0x1
write_32 0x1B 0x1
#Setting data register to 5
write_32 0x1C 0x5
#Writing the data to set DFE 1st tap value to 5
write_32 0x1A 0x1
Transceiver Reconfiguration Controller AEQ Registers
Adaptive equalization compensates for backplane losses and dispersion which degrade signal quality.
AEQ can be run once to help control the four-stage continuous time linear equalizer (CTLE), which is a
manual tool that compensates for backplane losses and dispersion.
The following table lists the direct AEQ registers that you can access using Avalon-MM reads and writes
on reconfiguration management interface.
Note: All undefined register bits are reserved.
16-24
Transceiver Reconfiguration Controller AEQ Registers
UG-01080
2015.01.19
Altera Corporation
Transceiver Reconfiguration Controller IP Core Overview