Altera Transceiver PHY IP Core - Manual (Page 492)

Standard PCS Parameters
This section illustrates the complete datapath and clocking for the Standard PCS and defines the
parameters available to enable or disable the individual blocks in the Standard PCS.
Figure 15-2: The Standard PCS Datapath
Transmitter PCS Transmitter PMA
Receiver PMA Receiver PCS
Cyclone V
FPGA Fabric
Byt
e O
rdering
RX Phase
Compens
ation
FIFO
Byt
e D
eserializ
er
8B/10B D
ec
oder
Ra
te Ma
tch FIFO
W
or
d A
ligner
Deserializ
er
CDR
TX Phase
Compensa
tion
FIFO
Byt
e S
erializ
er
8B/10B E
nc
oder
TX B
it Slip
Serializ
er
rx_serial_da
ta
tx_serial_da
ta
tx_parallel data
rx_parallel data
/2
/2
tx_coreclkin
rx_coreclkin
Recovered Clock
from Master Channel
Parallel Clock
Serial
Clock
Serial Clock
Parallel Clock
tx_clkout
rx_clkout
Note: For more information about the Standard PCS, refer to the PCS Architecture section in the
Transceiver Architecture in Cyclone V Devices.
The following table describes the general and datapath options for the Standard PCS.
UG-01080
2015.01.19
Standard PCS Parameters 15-9
Cyclone V Transceiver Native PHY IP Core Overview Altera Corporation
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