Altera Transceiver PHY IP Core User Manual
Page 506
Figure 15-3: Common Interface Ports
tx_pll_refclk[<r>-1:0]
tx_pma_clkout[<n>-1:0]
rx_pma_clkout[<n>-1:0]
rx_cdr_refclk[<r>-1:0]
Clock Input
& Output Signals
rx_seriallpbken[<n>-1:0]
rx_setlocktodata[<n>-1:0]
rx_setlocktoref[<n>-1:0]
pll_locked[<p>-1:0]
rx_is_lockedtodata[<n>-1:0]
rx_is_lockedtoref[<n>-1:0]
rx_clkslip[<n>-1:0]
Control &
Status Ports
pll_powerdown[<p>-1:0]
tx_analogreset[<n>-1:0]
tx_digitalreset[<n>-1:0]
rx_analogreset[<n>-1:0]
rx_digitalreset[<n>-1:0]
Resets
tx_parallel_data[<n>44-1:0]
rx_parallel_data[<n>64-1:0]
Parallel
Data Ports
tx_serial_data[<n>-1:0]
rx_serial_data[<n>-1:0]
TX & RX
Serial Ports
reconfig_to_xcvr [(<n>70-1):0]
reconfig_from_xcvr [(<n>46-1):0]
tx_cal_busy[<n>-1:0]
rx_cal_busy[<n>-1:0]
Reconfiguration
Interface Ports
Native PHY Common Interfaces
ext_pll_clk[<p>-1:0]
Table 15-16: Native PHY Common Interfaces
Name
Direction
Description
Clock Inputs and Output Signals
tx_pll_refclk[<r>-1:0]
Input
The reference clock input to the TX PLL.
rx_pma_clkout[<n>-1:0]
Output
RX parallel clock (recovered clock)
output from PMA
rx_cdr_refclk[<n>-1:0]
Input
Input reference clock for the RX PFD
circuit.
ext_pll_clk[ <p> -1:0]
Input
This optional signal is created when you
select the Use external TX PLL option. If
you instantiate a fractional PLL which is
external to the Native PHY IP, then
connect the output clock of this PLL to
ext_pll_clk
.
Resets
UG-01080
2015.01.19
Common Interface Ports
15-23
Cyclone V Transceiver Native PHY IP Core Overview
Altera Corporation