Altera Transceiver PHY IP Core - Manual (Page 472)

Name Dir Synchro‐
nous to tx_
10g_
coreclkin/
rx_10g_
coreclkin
Description
tx_10g_control
[9<n>-1:0]
(continued)
• [2]: Inversion signal, must always be set to 1'b0.
• [1]: Sync Header, 1 indicates a control word
• [0]: Sync Header, 1 indicates a data word
10G BaseR mode:
• [8]: Active-high synchronous error insertion
control signal
• [7]: MII control signal for
tx_data[63:56]
• [6]: MII control signal for
tx_data[55:48]
• [5]: MII control signal for
tx_data[47:40]
• [4]: MII control signal for
tx_data[39:32]
• [3]: MII control signal for
tx_data[31:24]
• [2]: MII control signal for
tx_data[23:16]
• [1]: MII control signal for
tx_data[15:8]
• [0]: MII control signal for
tx_data[7:0]
Basic mode: 67-bit word width:
• [8:3]: Not used
• [2]: Inversion Bit - must always be set to 1'b0.
• [1]: Sync Header, 1 indicates a control word)
• [0]: Sync Header, 1 indicates a data word)
Basic mode: 66-bit word width:
• [8:2]: Not used
• [1]: Sync Header, 1 indicates a control word)
• [0]: Sync Header, 1 indicates 1 data word)
Basic mode: 64-bit, 50-bit, 40-bit, 32-bit word
widths:
[8:0]: Not used
UG-01080
2015.01.19
10G PCS Interface 14-61
Arria V GZ Transceiver Native PHY IP Core Altera Corporation
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