Table 5: register revision (0x0001), Table 6: register build (0x0002:0x0003) – BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual

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Table 5: register revision (0x0001), Table 6: register build (0x0002:0x0003) | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual | Page 19 / 126 Table 5: register revision (0x0001), Table 6: register build (0x0002:0x0003) | BECKHOFF EtherCAT IP Core for Xilinx FPGAs v2.04e User Manual | Page 19 / 126
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